AT32UC3C2512C-A2UT【PDF 8/110 页】IC MCU AVR32 512K FLASH 64TQFP

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2011 Microchip Technology Inc.

DS70150E-page 105

dsPIC30F6010A/6015

15.13 PWM Update Lockout

For a complex PWM application, the user may need to

write up to four Duty Cycle registers and the Time Base

Period register, PTPER, at a given time. In some appli-

cations, it is important that all buffer registers be written

before the new duty cycle and period values are loaded

for use by the module.

The PWM update lockout feature is enabled by setting

the UDIS control bit in the PWMCON2 SFR. The UDIS

bit affects all Duty Cycle Buffer registers and the PWM

time base period buffer, PTPER. No duty cycle

changes or period value changes will have effect while

UDIS = 1.

If the IUE bit is set, any change to the Duty Cycle reg-

isters will be immediately updated regardless of the

UDIS bit state. The PWM Period register updates

(PTPER) are not affected by the IUE control bit.

15.14 PWM Special Event Trigger

The PWM module has a special event trigger that

allows A/D conversions to be synchronized to the PWM

time base. The A/D sampling and conversion time may

be programmed to occur at any point within the PWM

period. The special event trigger allows the user to min-

imize the delay between the time when A/D conversion

results are acquired and the time when the duty cycle

value is updated.

The PWM special event trigger has an SFR named

SEVTCMP, and five control bits to control its operation.

The PTMR value for which a special event trigger

should occur is loaded into the SEVTCMP register.

When the PWM time base is in an Up/Down Counting

mode, an additional control bit is required to specify the

counting phase for the special event trigger. The count

phase is selected using the SEVTDIR control bit in the

SEVTCMP SFR. If the SEVTDIR bit is cleared, the spe-

cial event trigger will occur on the upward counting

cycle of the PWM time base. If the SEVTDIR bit is set,

the special event trigger will occur on the downward

count cycle of the PWM time base. The SEVTDIR

control bit has no effect unless the PWM time base is

configured for an Up/Down Counting mode.

15.14.1

SPECIAL EVENT TRIGGER

POSTSCALER

The PWM special event trigger has a postscaler that

allows a 1:1 to 1:16 postscale ratio. The postscaler is

configured by writing the SEVOPS<3:0> control bits in

the PWMCON2 SFR.

The special event output postscaler is cleared on the

following events:

Any write to the SEVTCMP register

Any device Reset

15.15 PWM Operation During CPU Sleep

Mode

The Fault A and Fault B input pins have the ability to

wake the CPU from Sleep mode. The PWM module

generates an interrupt if either of the Fault pins is

driven low while in Sleep.

15.16 PWM Operation During CPU Idle

Mode

The PTCON SFR contains a PTSIDL control bit. This

bit determines if the PWM module will continue to

operate or stop when the device enters Idle mode. If

PTSIDL = 0, the module will continue to operate. If

PTSIDL = 1, the module will stop operation as long as

the CPU remains in Idle mode.

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